The present inventions relate to memories made in integrated circuit form, and especially electrically nonvolatile memories that are erasable or non-erasable and reprogrammable or non-reprogrammable.
One of the problems encountered in the manufacture of such memories, when they comprise a very large number of cells, is the need to test them completely before delivering them. The memories are tested in their blank state, to ascertain that there are absolutely no flawed cells.
In the electrically programmable cells that are commonly manufactured at present, the cells are constituted by floating-gate transistors. When the cells are blank, there are no charges stored in the floating gate. If the cell is biased with appropriate reading potentials, the cell should let a current through. If, on the contrary, the cell is programmed, it no longer lets any current through under the same conditions of bias.
However, the current that flows through a blank cell is very weak. To detect it in reading mode, the procedure uses differential reading, by comparison with a reference cell identical to the memory cells. If I is used to designate the current that flows in a cell in reading mode, this current I has a value I.sub.1 if the cell is blank and I.sub.2 (practically zero) if the cell is programmed. A comparison is made, in a differential current comparator, of the current I.sub.ref which flows through the (blank) reference cell with a current that is the sum I.sub.+Ibias of the current I in the cell to be read and of a bias current I.sub.bias. The current I.sub.ref is in principle equal to I.sub.1 (the current in a blank cell). The bias I.sub.bias is chosen so as to be substantially equal to (I.sub.2 -I.sub.1)/2, i.e. in practice I.sub.ref /2. In this way, if the current I read in a cell is slightly lower than I.sub.ref /2, the result of the comparison will be in a first direction and the cell will be considered to be in the programmed state. If, on the contrary, the current I is above I.sub.ref /2, the result of the comparison will be in the other direction and the cell will be considered to be blank.
The bias current I.sub.bias will therefore be aimed at facilitating the comparison between the current of the cell to be read and the reference cell.
During the testing of the memories, the memory is read according to the same principle of differential reading.
It has been perceived, according to the invention, that memories may prove to be flawed during use even though the cells have been tested rigorously one by one. These flaws have been attributed notably to faulty contacts which may occur between the memory cells and a conductor (bit line) to which these cells are connected to transmit the current representing the state of the cell. The contact-forming operation is indeed a delicate operation in the manufacturing process. Not only can the contacts be flawed at the outset, but they can also deteriorate through (natural or enforced) aging.
An aim of the invention is to provide for improved memory testing, to achieve more efficient elimination of chips which include flawed cells, notably as regards the contacts.
According to the invention, it is proposed that the memory should be provided with means to give the bias current a lower value in testing mode than in normal reading mode.
Thus, only the cells for which the reading current in the blank state is high enough will successfully pass the test to verify the blank state. Those with a reading current that is excessively low (albeit sufficient in normal reading mode) will be rejected. This excessively low value will be considered to denote the likely presence of a faulty contact which, in the process of aging, risks causing an erroneous operation of the memory. The cell or the memory will therefore be rejected.
Thus, the electrically programmable integrated memory according to the invention, in which the state of a cell is read by comparison between a current absorbed by a reference cell and the sum of the current absorbed by the cell to be read and a bias current I.sub.bias produced inside the integrated circuit, advantageously comprises means for the reduction, in test mode, of the value of the bias current, and for the reading of the state of the cells with this reduced value of the bias current.
The bias current in testing mode is preferably about half the bias current in normal reading mode.